diff --git a/kernel-open/nvidia-drm/nvidia-drm-linux.c b/kernel-open/nvidia-drm/nvidia-drm-linux.c index 3cb1815..209cb46 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-linux.c +++ b/kernel-open/nvidia-drm/nvidia-drm-linux.c @@ -31,7 +31,7 @@ MODULE_PARM_DESC( modeset, - "Enable atomic kernel modesetting (1 = enable, 0 = disable (default))"); + "Enable atomic kernel modesetting (1 = enable (default), 0 = disable)"); module_param_named(modeset, nv_drm_modeset_module_param, bool, 0400); #if defined(NV_DRM_FBDEV_AVAILABLE) diff --git a/kernel-open/nvidia-drm/nvidia-drm-os-interface.c b/kernel-open/nvidia-drm/nvidia-drm-os-interface.c index a6b3525..25ded0f 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-os-interface.c +++ b/kernel-open/nvidia-drm/nvidia-drm-os-interface.c @@ -38,7 +38,7 @@ #include #endif -bool nv_drm_modeset_module_param = false; +bool nv_drm_modeset_module_param = true; bool nv_drm_fbdev_module_param = true; void *nv_drm_calloc(size_t nmemb, size_t size) diff --git a/src/common/displayport/src/dp_wardatabase.cpp b/src/common/displayport/src/dp_wardatabase.cpp index a205fab..04f1c62 100644 --- a/src/common/displayport/src/dp_wardatabase.cpp +++ b/src/common/displayport/src/dp_wardatabase.cpp @@ -542,6 +542,19 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen } break; + // Bigscreen Beyond VR headset + case 0x2709: + if (ProductID == 0x1234) + { + // + // The Bigscreen Beyond connects via a link box (DP -> optical). + // Force 4 lanes HBR2 to ensure sufficient bandwidth. + // + this->WARFlags.forceMaxLinkConfig = true; + DP_PRINTF(DP_NOTICE, "DP-WAR> Force maximum link config for Bigscreen Beyond VR headset."); + } + break; + // CMN case 0xAE0D: if (ProductID == 0x1747) diff --git a/src/common/modeset/timing/nvt_dsc_pps.c b/src/common/modeset/timing/nvt_dsc_pps.c index 0f6ba54..94e33b4 100644 --- a/src/common/modeset/timing/nvt_dsc_pps.c +++ b/src/common/modeset/timing/nvt_dsc_pps.c @@ -191,12 +191,12 @@ static const NvU8 minqp444_8b[15][37]={ ,{ 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0} ,{ 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0} ,{ 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0} - ,{ 6, 5, 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0} + ,{ 6, 5, 5, 4, 3, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0} // [9] col4: 4->3 (VESA DSC 1.1) ,{ 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 0} ,{ 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 0} ,{ 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 0} - ,{ 9, 9, 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 1, 1, 1} - ,{14,14,13,13,12,12,12,12,11,11,10,10,10,10, 9, 9, 9, 8, 8, 8, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3} + ,{ 9, 9, 9, 9, 7, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 1, 1, 1} // [13] col4: 8->7 (VESA DSC 1.1) + ,{14,14,13,13,13,12,12,12,11,11,10,10,10,10, 9, 9, 9, 8, 8, 8, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3} // [14] col4: 12->13 (VESA DSC 1.1) }; static const NvU8 maxqp444_8b[15][37]={ @@ -210,11 +210,11 @@ static const NvU8 maxqp444_8b[15][37]={ ,{10,10, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 6, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1} ,{11,11,10,10, 9, 9, 9, 9, 9, 9, 8, 8, 8, 7, 7, 6, 6, 5, 5, 5, 5, 5, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1} ,{12,11,11,10,10,10, 9, 9, 9, 9, 9, 9, 9, 8, 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1} - ,{12,12,11,11,10,10,10,10,10,10, 9, 9, 9, 8, 8, 7, 7, 6, 6, 6, 5, 5, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1} - ,{12,12,12,11,11,11,10,10,10,10, 9, 9, 9, 9, 8, 8, 8, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 1} - ,{12,12,12,12,11,11,11,11,11,10,10, 9, 9, 9, 8, 8, 8, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 1} - ,{13,13,13,13,12,12,11,11,11,11,10,10,10,10, 9, 9, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 4, 4, 4, 4, 3, 3, 2, 2, 2} - ,{15,15,14,14,13,13,13,13,12,12,11,11,11,11,10,10,10, 9, 9, 9, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 5, 4, 4, 4, 4} + ,{12,12,11,11,11,10,10,10,10,10, 9, 9, 9, 8, 8, 7, 7, 6, 6, 6, 5, 5, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1} // [10] col4: 10->11 (VESA DSC 1.1) + ,{12,12,12,11,12,11,10,10,10,10, 9, 9, 9, 9, 8, 8, 8, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 1} // [11] col4: 11->12 (VESA DSC 1.1) + ,{12,12,12,12,13,11,11,11,11,10,10, 9, 9, 9, 8, 8, 8, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 1} // [12] col4: 11->13 (VESA DSC 1.1) + ,{13,13,13,13,13,12,11,11,11,11,10,10,10,10, 9, 9, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 4, 4, 4, 4, 3, 3, 2, 2, 2} // [13] col4: 12->13 (VESA DSC 1.1) + ,{15,15,14,14,15,13,13,13,12,12,11,11,11,11,10,10,10, 9, 9, 9, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 5, 4, 4, 4, 4} // [14] col4: 13->15 (VESA DSC 1.1) }; static const NvU8 minqp444_10b[15][49]={ @@ -938,7 +938,7 @@ DSC_PpsCalcRcParam //else { const NvU32 ofs_und6[] = { 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 }; - const NvU32 ofs_und8[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; + const NvU32 ofs_und8[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 }; // [11]: -10->-12 (VESA DSC 1.1) const NvU32 ofs_und12[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 }; const NvU32 ofs_und15[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 }; diff --git a/src/nvidia-modeset/src/nvkms-evo3.c b/src/nvidia-modeset/src/nvkms-evo3.c index 27e533a..3b76261 100644 --- a/src/nvidia-modeset/src/nvkms-evo3.c +++ b/src/nvidia-modeset/src/nvkms-evo3.c @@ -7816,10 +7816,13 @@ static void EvoSetDpDscParams(const NVDispEvoRec *pDispEvo, nvAssert(pDscInfo->type == NV_DSC_INFO_EVO_TYPE_DP); - // XXX: I'm pretty sure that this is wrong. - // BitsPerPixelx16 is something like (24 * 16) = 384, and 2 << (384 - 8) is - // an insanely large number. - flatnessDetThresh = (2 << (pDscInfo->dp.bitsPerPixelX16 - 8)); /* ??? */ + // Fix: use bits_per_component from PPS byte 3 [7:4], not bitsPerPixelX16. + // DSC spec: flatness_det_thresh = 2 << (bpc - 8). + // PPS DW[0] packs bytes [3][2][1][0] as [31:24][23:16][15:8][7:0]. + { + NvU32 bpc = (pDscInfo->dp.pps[0] >> 28) & 0xF; // PPS byte 3 bits[7:4] + flatnessDetThresh = (bpc >= 8) ? (2 << (bpc - 8)) : 2; + } nvAssert((pDscInfo->dp.dscMode == NV_DSC_EVO_MODE_DUAL) || (pDscInfo->dp.dscMode == NV_DSC_EVO_MODE_SINGLE)); diff --git a/src/nvidia-modeset/src/nvkms-evo4.c b/src/nvidia-modeset/src/nvkms-evo4.c index 3159086..bd498a5 100644 --- a/src/nvidia-modeset/src/nvkms-evo4.c +++ b/src/nvidia-modeset/src/nvkms-evo4.c @@ -1409,10 +1409,13 @@ static void EvoSetDpDscParamsC9(const NVDispEvoRec *pDispEvo, nvAssert(pDscInfo->type == NV_DSC_INFO_EVO_TYPE_DP); - // XXX: I'm pretty sure that this is wrong. - // BitsPerPixelx16 is something like (24 * 16) = 384, and 2 << (384 - 8) is - // an insanely large number. - flatnessDetThresh = (2 << (pDscInfo->dp.bitsPerPixelX16 - 8)); /* ??? */ + // Fix: use bits_per_component from PPS byte 3 [7:4], not bitsPerPixelX16. + // DSC spec: flatness_det_thresh = 2 << (bpc - 8). + // PPS DW[0] packs bytes [3][2][1][0] as [31:24][23:16][15:8][7:0]. + { + NvU32 bpc = (pDscInfo->dp.pps[0] >> 28) & 0xF; + flatnessDetThresh = (bpc >= 8) ? (2 << (bpc - 8)) : 2; + } nvAssert((pDscInfo->dp.dscMode == NV_DSC_EVO_MODE_DUAL) || (pDscInfo->dp.dscMode == NV_DSC_EVO_MODE_SINGLE));